In U.S. Pat. No. 6,888,196, a conventional structure of power semiconductor device is disclosed, as shown in FIG. 1, wherein an N-channel trench MOSFET comprising a plurality of trenched gates 110 surrounded by n+ source regions 112 encompassed in P body regions 114 is formed in an N epitaxial layer 102 over an N+ substrate 100. To connect said source regions 112 and said body regions 114 to a source metal 122, a trenched source-body contact 118 with vertical sidewall is employed penetrating through a contact interlayer 120, said n+ source regions 112 and extending into said P body regions 114. Furthermore, a p+ body ohmic contact doped region 116 is implanted surrounding bottom of said trenched source-body contact to decrease a contact resistance between said P body regions 114 and said trenched source-body contact 118.
The conventional structure in FIG. 1 is accoutering a technical difficulty which is that avalanche always occurs near bottom of said trenched gates 110, causing a hazardous condition to the power semiconductor device. As we all know that, in the trench MOSFET shown in FIG. 1, a avalanche current lay (illustrated in FIG. 1) flows between said trenched gates 110 and said source-body contact 118, triggering turning-on of a parasitic bipolar transistor (illustrated in FIG. 1) when Iav*Rb>0.7V, wherein Rb is a resistance between said p+ body ohmic contact doped region 116 and channel region near said trenched gates 110. As is known to all that, the doping concentration of said p+ body ohmic contact doped region 116 is higher than that of said P body region 114 (please refer to FIG. 2 for Y1-Y1′ cross section of FIG. 1), which is helpful to decrease resistance Rb, however, as the sidewall of said trenched source-body contact is perpendicular to the front surface of said N epitaxial layer 102, when carrying out implantation through a contact trench, said p+ body ohmic contact doped region 116 can be formed only surrounding bottom of said trenched source-body contact, resulting in a high resistance Rb underneath said n+ source regions 112. Therefore, said parasitic bipolar transistor is easily to be triggered turning on due to the high resistance Rb, thus weakening the avalanche capability of the trench MOSFET.
FIG. 3 shows another trench MOSFET in prior art disclosed in U.S. Patent No. 20080890357. Comparing to FIG. 1, the trench MOSFET in FIG. 3 comprises a plurality of trenched gates 130 having terrace gate structure for gate resistance reduction, wherein top surface of gate conductive layer filled in gate trenches is higher than the sidewall. However, the limitation of poor avalanche capability discussed above is still pronounced in this structure due to the easily turning-on of a parasitic bipolar transistor and the occurring of avalanche near bottom of said trenched gates 130.
For other power semiconductor power device, for example trench IGBTs, the same disadvantage of poor avalanche capability is also affecting the performance of the power semiconductor device.
Accordingly, it would be desirable to provide new and improved power semiconductor devices to avoid the constraint discussed above.